Regviz

Silicon Labs /BGM220SC22WGA /MODEM_S /PRE

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PRE

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32BG22C224F512GM32/MODEM_S/PRE#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BASE0BASEBITS 0 (OUTER)PRESYMB4FSK 0PREERRORS 0 (DSSSPRE)DSSSPRE 0 (FSK2)SYNCSYMB4FSK 0TXBASES

SYNCSYMB4FSK=FSK2, PRESYMB4FSK=OUTER

Description

No Description

Fields

BASE

Preamble base
BASEBITS

BASE bits
PRESYMB4FSK

Preamble symbols 4-FSK

0 (OUTER): Symbols corresponding to +/- 3dev.

1 (INNER): Symbols corresponding to +/- dev.
PREERRORS

Preamble errors
DSSSPRE

DSSS preamble
SYNCSYMB4FSK

Sync symbols 4FSK

0 (FSK2): The syncword is 2FSK modulated. Each bit in SYNCn is encoded as a positive or negative deviation. The deviation is controlled by PRESYMB4FSK.

1 (FSK4): The syncword is 4FSK modulated. Every two bits in SYNCn are encoded as a 4FSK symbol.
TXBASES

TX bases

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data